Objectives

The objective of the MOSART project is to develop a flexible, modular, multi-core on-chip platform (Figure 1) architecture and associated exploration design methods and tools, to allow the scaling of the platform and optimization of its constituent elements for various embedded, multimedia and wireless communication applications.

Multi-core on-chip platform architecture. In MOSART we will develop an architectural template that will have sufficient computing power to meet several next generation high-end applications from switching, multimedia, security and wireless concurrently. In the interest of improving design productivity and to gain flexibility, MOSART will primarily rely on a cluster of distributed ASIPs to provide the computing power. To address the memory and interconnect challenges, MOSART develops a distributed memory architecture that is tightly integrated with a Network-on-Chip (NoC) interconnect backbone.

Data Management and middleware. To effectively utilize the distributed architecture and make the development cycle more modular, MOSART will develop middleware services for memory management for run-time data allocation and access scheduling. This middleware will provide an abstract data type library offering optimised data types to the applications running on the platform. Additionally, a run-time data allocator will be in charge of the data allocation over the distributed memory of the NoC platform. These multi-layer services will be modelled in such a way, in order to serve the separation of the platform from applications.

Design methods and tools. A design methodology will be developed for system level exploration of the algorithmic and architectural space in terms of power, performance and cost. Towards this goal, methods will be developed to a) optimise and map of abstract data types and communication primitives to efficient distributed memory and interconnect architecture, b) extract parallelism from a single threaded specification and map the application to the architecture and c) match and customise cluster of ASIPs to the suite of applications. Existing and new tools that automate the design path as much as possible, from the algorithmic level of applications down to the details of IP processing cores, the custom processing blocks and their memory interfaces will be evaluated and, if suitable, will be exploited.

Demanding application cases. Two representative application cases from the domain of wireless communications will be used for validating the architecture and the design methodology.

Addressing ARTEMIS and HIPEAC challenges. The proposed work being done within MOSART is also inline with the HIPEAC roadmap [http://www.hipeac.net] and ARTEMIS priorities [http://www.artemis-office.org], as listed in the respective columns of Table 1.

Table 1. List of Themes and Key Challenges addressed in MOSART from HiPEAC roadmap and ARTEMIS Strategic Research Agenda.

HIPEAC Roadmap		ARTEMIS Research Priorities
Theme	Key Challenge	Research Priority	Topic
Multi-Core Architecture	2.2: On-Chip Interconnects and Memory System	Seamless Connectivity and Middleware	Middleware architectures
Interconnection Networks	3.2: Interconnect Power Consumption and Management 3.5: Interconnect Design Space Exploration	Reference design and Architectures	High Performance embedded Computing Low Power
Programming Models and Tools	4.3: Adaptive Data Structures	Embedded System Architecture	Architecture: architectural services Networking: on-chip networks, communication primitives
Run-time Systems	6.2: Power-Aware Run-time Systems

MOSART provides its unique holistic treatment of computational, storage and interconnect resources, as shown in Figure 2, whereas other attempts have treated individual dimensions. Furthermore, we also treat the three issues at system level, middleware level and architectural level. Lastly, we also holistically consider power, performance and cost metrics. This creates a three-dimensional solutions space for MOSART, as shown in Figure 2.